Fourth High-Performance Grid Computing Workshop

March 26, 2007, Long Beach, California, USA

 
in conjunction with
 

International Parallel and Distributed Processing Symposium - IPDPS 2007
March 26-30, 2007, Long Beach, California, USA

Background

Computational grids allow the federation of significant computational and storage resources to solve challenging problems in science, engineering, medicine, finance, and entertainment. Involvement of multi-core platforms and wireless communications in the traditional grids comprised of clusters, workstations, and supercomputers pose new challenges to manage the grids and open new opportunities in using them. The High Performance Grid Computing workshop provides a forum for presenting research results on most aspects of grid computing, with a focus on performance, in the following areas: Applications, Benchmarking, Infrastructure, Management and Scheduling, Partitioning and Load Balancing, and Programming Models.

Intel Best Paper Award

• novelty of the results
• efficiency of using the grid
• achieved performance gains in the problem solved on the grid
• quality of the presentation

Intel, the Intel logo, Intel. Leap ahead. and Intel. Leap ahead. logo
are trademarks or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.

• Applications: Theory and practice of composing grid applications consisting of multiple interacting tasks. Solution of large problems on  grids. 
• Benchmarking: Grid measurement technology for evaluating performance of grid hardware and middleware; benchmark results. 
• Infrastructure: Implementation and evaluation of computational grid middleware.
• Management and Scheduling: Management, monitoring, resource allocation, scheduling, and metascheduling.
• Partitioning and Load Balancing: Partitioning applications for computational grids for achieving high performance, and load balancing of grid applications.
• Multi-core processors as grid components.
• Programming Models: Methods for remote execution and intertask communications.

Paper Submission

We invite submissions not exceeding eight single-spaced pages. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. Each paper will be refereed by at least three independent
reviewers. Paper submission indicates the intention of the author to present the paper at the HPGC workshop at IPDPS 2007.

Click here to submit your paper.

Submission deadline: November 17, 2006. There will be NO extension of this deadline. Authors will be notified by December 18, 2006.

The HPGC workshop proceedings will be published by the IEEE Computer Society along with the IPDPS conference proceedings. 

Workshop Organizers

• Eric Aubanel, University of New Brunswick, Canada

• Virendra C. Bhavsar, University of New Brunswick, Canada

• Michael Frumkin, Intel Corporation, USA

Program Committee

• Akshai Aggarwal, University of Windsor, Windsor, ON, Canada

• Nikos P. Chrisochoides, College of William and Mary, Wlliamsburg, VA, USA

• Anthony T. Chronopoulos, Univ. of Texas at San Antonio, USA

• Weichang Du, University of New Brunswick, Canada

• Wolfgang Gentzsch, German D-Grid Initiative
• Alexey Lastovetsky, University College Dublin, Ireland
• Thuy T. Le, San Jose State University, USA
• Xiaolin (Andy) Li, Oklahoma State University, USA
• Gabriel Mateescu, National Research Council, Ottawa, Canada
• Francois Pellegrini, INRIA and LaBRI, Universite Bordeaux, France
• Sushil Prasad, Georgia State University, USA
• Andrew Rau-Chaplin, Dalhousie University, Canada
• Thomas Rauber, University of Bayreuth, Germany

• Ruth Shaw, University of New Brunswick, Canada

• Simon Chong-Wee See, Sun Asia Pacific Science and Technology Center and Nanyang Technological University
• Allan Snavely, San Diego Supercomputing Center, La Jolla, CA, USA

• Laurence T. Yang, St. Francis Xavier University, Canada

• Rob F. Van Der Wijngaart, Intel Corporation, USA

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